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To meet the rapidly growing demand for AI capacity, AMD has officially announced a major financial injection of more than $10 billion. The funds are being invested in Taiwan’s infrastructure and ecosystem to deepen strategic collaboration with partners and significantly increase the production of advanced advanced packaging, which is critical to building the next generation of AI infrastructure.
By joining forces with Taiwanese and other international partners, the company is actively developing state-of-the-art semiconductor crystal manufacturing, packaging, and overall production processes that guarantee higher performance, significantly reduced power consumption, and accelerated deployment of new types of computing systems.
According to AMD Chairman and CEO Dr. Lisa Su, the process of introducing artificial intelligence in the world is constantly accelerating, which is why global consumers are forced to quickly increase their hardware capacity to meet the growing demands for computing. She emphasized that the combination of the company’s advanced high-performance systems with the capabilities of the Taiwanese ecosystem and the potential of key global partners allows for the creation of ready-made integrated solutions at the server rack level, which allows customers to launch next-generation AI computing systems much faster. The current multi-billion dollar funding announcement clearly demonstrates AMD’s commitment to strengthening its leadership position by entering into strategic alliances that drive forward the silicon crystal, packaging and fabless innovations that are essential to the future of computing hardware.
As part of the EFB ecosystem development, AMD is working with well-known Taiwanese companies ASE and SPIL, as well as other semiconductor industry players, to create and certify a new 2.5D interconnect architecture at the substrate level. EFB’s architectural solution significantly increases the bandwidth of internal communication channels and makes power consumption much more efficient, which is a basic requirement for full support of the Venice codenamed CPUs.
These qualitative improvements directly translate into more agile and energy-efficient computing systems that can deliver record performance for every watt of power consumed, successfully fitting into the real-world constraints of power and cooling in data centers. At the same time, in the field of panel-based innovation, a significant success was achieved in cooperation with PTI, which resulted in the official approval of the semiconductor industry’s first 2.5D panel-based EFB interconnect technology.
The global partner environment is also significantly accelerating the practical implementation of the AMD Helios rack-level server platform, which is scheduled for release in the second half of 2026, which will be a significant step towards creating a fully commercially ready AI infrastructure. Leading developers and contract manufacturers of equipment, including Sanmina, Wiwynn, Wistron, and Inventec, are actively involved in the design and preparation for mass production of AMD Helios systems. These systems are based on AMD Instinct MI450X GPU accelerators, sixth-generation AMD EPYC CPUs, modern networking solutions, and use the AMD ROCm open software stack, which helps to successfully scale the platform from initial drawings to high-volume assembly line production. The AMD Helios server architecture is designed to provide an unprecedented level of performance in artificial intelligence tasks due to advances in computing power, expanded connection bandwidth, increased RAM, and deep integration of system components.
At the same time, AMD officially announced that its future AMD EPYC server CPU, codenamed Venice, is entering volume production at TSMC’s Taiwan facilities using the ultra-modern 2-nanometer process technology, and that it plans to start production of these chips at TSMC’s US fab in Arizona. This important milestone in the implementation of the company’s strategic plan for the development of server processors demonstrates a systematic movement towards achieving the highest performance and energy efficiency, which are vital for modern cloud systems, enterprise platforms and AI infrastructure. The Venice processor is the first-ever HPC product to go into mass production on TSMC’s advanced 2-nanometer fab standards.
According to Dr. Lisa Su, the launch of Venice chips on TSMC’s 2nm fabs is a key milestone in bringing the era of future computing closer, as customers are looking for solutions that can move from concept to commercial application as quickly as possible amid the rapidly increasing complexity of artificial intelligence and agent-based systems. She noted that the deep collaboration with TSMC allows AMD to bring advanced computing architectures to the market at the speed and volume required by today’s market realities.
As artificial intelligence applications evolve from basic training and logical inference to complex autonomous AI agents, the role of the CPU in the architecture becomes increasingly important, as it is tasked with coordinating data flows, managing network interfaces, storage, security, and overall orchestration of processes within the data center. The start of mass production of Venice comes amid the constant strengthening of the company’s position in the server hardware market, which clearly reflects the growing interest of businesses in EPYC platforms to support modern cloud, corporate, scientific and AI projects.
In addition, AMD is going to introduce TSMC’s 2-nanometer process to other products in its server line, announcing the Verano processor, which will represent the sixth generation of EPYC chips and will focus on achieving absolute leadership in terms of performance, price and power consumption. Designed specifically for cloud infrastructures and artificial intelligence systems, the Verano chip is designed to extend the platform’s capabilities with advanced memory technologies, including LPDDR standards, to deliver the computing power and bandwidth required by today’s power-hungry applications.
AMD and TSMC’s collaboration covers a huge range of technology solutions that enable data center computing to scale, from the use of 2nm lithography for processor cores to the application of unique bulk crystal packaging techniques such as SoIC-X and CoWoS-L, which are being actively implemented in the accelerator and server portfolio. With the launch of Venice production on the 2nm process, AMD is not only updating the processor base for artificial intelligence infrastructure, but also continues to leverage TSMC’s industry leadership in semiconductor manufacturing and packaging to create the most integrated world-class computing platforms.
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