Atomic horizon: how humanity is pushing chips to the limits of possibility

In the world of computer chips, quality is traditionally linked to measurable performance: more cores, higher clock speeds (GHz), and greater FLOPS are all desirable attributes. However, in semiconductor manufacturing, a different – and often opposite – metric dominates: the process node. The smaller the node, the better the potential outcome. Measured in nanometers (nm), this metric is currently driving intense excitement around 3 nm and 2 nm lithography standards.

The primary driver of transistor miniaturization is no longer mobile devices but the AI sector. The explosive demand for AI accelerators and high-performance computing (HPC) hardware for training large language models (LLMs) has turned advanced silicon manufacturing into a strategic asset and a critical bottleneck limiting global computational capacity. Major tech companies are investing heavily in the development and acquisition of chips that power AI applications.

Today, I invite you to dive with me into a detailed analysis of the “nanometer dilemma”: we’ll explore how EUV photolithography works, why smaller nodes are considered the “holy grail,” and which engineering and economic challenges will shape the future of computing down to 2 nm.

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Significance of metric: from physical measurement to marketing benchmark

Before diving into conceptual aspects, it’s important to recognize the fundamental role of CPU architecture. The transistor remains a critical structural element. Groups of transistors perform all computational and logical operations, as well as data storage functions within a chip, making their design central to any processor’s performance and efficiency.

One of the most heavily marketed terms in chip manufacturing is the transistor size, which is directly associated with the process node. Historically, it indicated the smallest distance within a transistor’s layout. Today, however, this definition has become blurred and less universal: the number printed on the packaging does not always reflect the exact geometry etched onto the silicon wafer. Different manufacturers measure their processes in varying ways, and node labels such as 5 nm or 3 nm no longer serve as precise indicators of physical scale. In other words, the process node in the modern context functions more as a marketing reference than as a reliable metric for directly comparing manufacturing techniques across companies.

Yet even with this ambiguity, the consistent reduction of nodes within a single manufacturer still reflects tangible improvements in transistor density, energy efficiency, and computational performance. For this reason, despite the conceptual imprecision, further miniaturization continues to be regarded as the “holy grail” of the semiconductor industry.

Hot Chips, Cold Calculations: How Miniaturization Transforms Processors

Reducing the size of electronic components has a direct impact on the physics of computation. In processors, no operation occurs instantaneously, and each transistor switching event consumes energy. Larger components take more time to change their logical state, leading to signal propagation delays and requiring higher power to drive current through the integrated circuit. Additionally, physically larger transistors occupy more space, making chips bulkier and limiting component density.

Let’s consider a historical example illustrated by three Intel processors: the 2006 Celeron, the 2004 Pentium M, and the original 1995 Pentium. They were manufactured using 65 nm, 90 nm, and 350 nm process nodes, respectively. Critical elements in the 28-year-old design were almost five times larger than those in the 17-year-old model. This miniaturization allowed a substantial increase in transistor count: the newer Celeron contained roughly 290 million transistors, while the original Pentium had just over 3 million – nearly a hundredfold difference.

The most striking aspect is energy efficiency. The Celeron generates about 30 W of heat, compared to the Pentium’s 12 W. This heat primarily results from electrical energy dissipation as current flows through the circuits. While 30 W is higher than 12 W, it must be considered that the Celeron contains almost 100 times more transistors. In other words, a smaller process node produces more compact chips, enables a higher transistor density for increased computational throughput, and simultaneously dissipates less energy per transistor as heat.

Given these advantages – faster switching speeds, increased computational power, and reduced heat generation – the natural question arises: why aren’t all chips manufactured using the smallest available process nodes?

Photolithography: How Chips Are Shaped

Photolithography is a fundamental process in semiconductor manufacturing. A light source passes through a photomask – a kind of selective filter that blocks or transmits energy in specific patterns. The light is then focused onto a small area of the silicon wafer, where it interacts with a specialized resist layer to define the contours of the chip’s components. The photomask functions similarly to bones in an X-ray image, creating a “shadow” or imprint of the internal structure.

In this process, visible light is not used because its wavelength is too long. Electromagnetic radiation is measured in nanometers (10⁻⁹ m): visible light ranges from 380–750 nm, whereas older processors – like the 2006 Celeron – were manufactured using a 65 nm process. This became possible thanks to ultraviolet (UV) radiation, which can be reduced to around 10 nm. Modern manufacturers such as Intel, TSMC, and GlobalFoundries use extreme ultraviolet (EUV) radiation with a wavelength of 13.5 nm, which has already become the standard for chips below 7 nm.

The shift to High-NA EUV technology enables the creation of components as small as 2 nm. Shorter wavelengths not only reduce the size of elements but also improve their precision, allowing transistors to be packed more densely. For example, TSMC and Samsung have already reached mass production at the 3 nm node and are moving toward 2 nm, implementing Gate-All-Around (GAA) transistors; Intel’s version is called RibbonFET. These structures allow efficient control of current leakage at the atomic level.

To put this into perspective: silicon atoms are spaced roughly 0.5 nm apart, so a 2 nm transistor element is literally just a few atoms wide.

Read also: What’s Wrong with AI Browsers?

Challenges of EUV Lithography: From Atomic Scales to Global Shortages

The shift to EUV lithography has introduced a new phase of miniaturization in the semiconductor industry, accompanied by significant engineering challenges. Manufacturers now work with features at the scale of a few atoms, while demand for 3 nm chips from companies such as Microsoft, Google, Amazon, and Meta places unprecedented pressure on global supply chains, spanning HBM memory, packaging, and the EUV systems themselves.

At Intel’s D1X flagship facility in Oregon, engineers operate a 165-ton High-NA EUV system from ASML, a machine capable of patterning features just a few tens of atoms wide. Intel faced prolonged challenges in stabilizing its 10 nm process, while GlobalFoundries encountered difficulties at the 7 nm node. These issues are not solely attributable to EUV technology, but the complexity of the process and the extremely small feature sizes make it highly sensitive to defects.

Shorter wavelengths correspond to higher photon energies, which increases the risk of material damage. EUV radiation requires extremely clean manufacturing environments, as even microscopic particles can cause defects. Additional challenges arise from diffraction limits and statistical variations, resulting in inconsistencies in the locations where energy is deposited on the chip layers.

Manufacturing Defects and Quantum-Level Challenges

Even without considering the complexity of EUV lithography, operating at atomic scales introduces fundamental issues: the flow of electricity and energy transfer no longer follow purely classical physical laws. Containing moving electrons within conductors placed close together is relatively straightforward at the macro scale, where a thick layer of insulation is sufficient.

At the scales currently used by Intel and TSMC, this task becomes extremely challenging, primarily because insulation layers are no longer thick enough, leading to unwanted effects such as electron tunneling. However, most current manufacturing issues are still attributable to the inherent complexity of EUV lithography itself. The transition to High-NA EUV requires even greater precision, necessitating the development and implementation of entirely new optical systems (lenses) and resist materials.

From Smartphones to AI: How the Economic Model of Chip Manufacturing Has Evolved

A major factor behind many manufacturing challenges in microelectronics is the underlying business model. Companies like Intel, TSMC, and their partners operate for profit, and the smaller the process node, the higher the production cost. The transition from 28 nm (Haswell) to 10 nm nearly doubled the cost of a wafer. Although higher chip yields offset some of these expenses, manufacturers still pass a significant portion of the costs onto consumers.

In the 2000s and 2010s, demand for smartphones and chips drove the reduction of process nodes, with IoT further supporting this progress. Manufacturers absorbed initial losses until production stabilized. However, in the AI era, the economics have shifted. The cost of wafers for 3 nm nodes exceeds $20,000, and developing a single chip can surpass $500 million. To reduce expenses, the industry has moved toward chiplet architectures, in which multiple smaller dies are integrated within a single package. This approach, pioneered by AMD, is now used by Intel, NVIDIA, and other AI accelerator manufacturers.

The primary semiconductor investments are now focused on AI hardware. Companies such as Microsoft, Google, Meta, and Amazon invest over $250 billion annually in data centers, creating a ripple effect across the entire supply chain – from fabrication and packaging to HBM memory and ASML EUV systems. The increasing stakes make the risks substantial: each new chip generation requires tens of billions in investment. This environment led GlobalFoundries to exit the race for leading-edge nodes, instead focusing on more stable 12–65 nm technologies for automotive and IoT markets.

Future Packed in Nanometers

Despite significant manufacturing and economic challenges, the semiconductor industry continues to advance. Samsung and TSMC are already producing chips using 3 nm processes, and the first 2 nm lines are beginning to scale up. Intel has also made a strong return to leading-edge nodes, implementing new transistor architectures such as RibbonFET and PowerVia.

At the same time, chip designers are laying the groundwork for future generations by combining components manufactured using different process nodes. A notable example is AMD’s chiplet strategy: in its third-generation Ryzen processors, 7 nm logic modules from TSMC were paired with a 14 nm memory controller from GlobalFoundries.

Today, this modular approach has become an industry standard. AMD’s Ryzen 9000 and EPYC Genoa server processors use 5 nm and 6 nm chiplets, while Intel’s Meteor Lake and Arrow Lake integrate 7 nm tiles through 3D Foveros packaging. This shift in chiplet architectures and three-dimensional integration is at least as significant for the industry’s development as the reduction of process nodes itself.

AI plays a dual role in this process, acting as both a catalyst and a tool. Machine learning helps optimize lithography processes, predict defects during the design phase, and increase the yield of functional chips per wafer. In effect, artificial intelligence simultaneously pushes manufacturing toward physical limits and teaches engineers to operate more efficiently under high-pressure conditions.

According to industry forecasts, the average cycle for process node reduction is approximately 4.5 years. By the end of 2025, Intel, TSMC, and Samsung are expected to have fully established 3 nm production, with the first 2 nm solutions entering the market in 2026–2027. Beyond this point, technological progress will advance not only “laterally” but also “vertically,” through transistor stacking and deep integration of AI acceleration into each silicon layer.

The outcome will be denser, cooler, and more efficient circuits, capable of enabling autonomous edge computing, powering microrobots, and supporting exaflop-scale data centers without straining power grids. We are on the verge of a breakthrough where computational power operates at the scale of individual atoms.

But as each transistor becomes smarter, each nanometer more expensive, and each silicon layer deeper, the question may no longer be how far we can go or how many atoms we can control – but which one might one day look back at us.

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Atomic Horizon: How Humanity Pushes Chips to Edge of Possibility